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      "timestamp": "2026-07-04T05:07:23.502+00:00",
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      "content": "Is that layer necessary ? What does it do exactly ?\nBecause I can draw a thin gate nmos (i.e. without the `DualGate` layer) without `LVPWELL` and it doesn't seem to change how it's extracted and it doesn't violate DRC either.",
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      "timestamp": "2026-07-04T05:36:36.598+00:00",
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      "content": "I believe `LVPWELL` is used inside deep nwells to create an isolated pwell for nmos with bulk connections other than ground.",
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      "content": "Ok, so when outside deep-nwell it doesn't matter. Good to know ! Tx.",
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